drm/amd/powerplay: fix vce cg logic error on CZ/St.
authorRex Zhu <Rex.Zhu@amd.com>
Tue, 10 Jan 2017 11:26:49 +0000 (19:26 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 5 Jul 2017 12:40:25 +0000 (14:40 +0200)
commitf275ac7fc5d2b6013980864f14d1ced016211349
tree7ed27549a3b143ff01d394800ee8883160026993
parent77e82094a3c9d3ca8308a48a4b11037c6234a262
drm/amd/powerplay: fix vce cg logic error on CZ/St.

[ Upstream commit 3731d12dce83d47b357753ffc450ce03f1b49688 ]

can fix Bug 191281: vce ib test failed.

when vce idle, set vce clock gate, so the clock
in vce domain will be disabled.
when need to encode, disable vce clock gate,
enable the clocks to vce engine.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c