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[AMDGPU] Ensure there are enough registers for wave dispatch
authorTim Renouf <tpr.llvm@botech.co.uk>
Wed, 11 Apr 2018 14:02:41 +0000 (14:02 +0000)
committerTim Renouf <tpr.llvm@botech.co.uk>
Wed, 11 Apr 2018 14:02:41 +0000 (14:02 +0000)
commitf26b723491ee2d998f2a44001005318f6c171243
treef0fdf72925d15ab534572f9beaa878baed6aa854tree | snapshot
parent5782ec29abd5719f6cdd666c86a9e4c6ea0727a8commit | diff
[AMDGPU] Ensure there are enough registers for wave dispatch

Summary:
This fixes the number of SGPRs and VGPRs in the *_RSRC1 register to
allow for registers set up in wave dispatch, even if those registers are
not used in the shader.

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45503

Change-Id: I6575f0e0d2a528d1319d0b289f0ebe4510fa5771
llvm-svn: 329808
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll [new file with mode: 0644] blob
Domain: System / Toolchain;