[SVE][CodeGen] Lower scalable integer vector reductions
authorKerry McLaughlin <kerry.mclaughlin@arm.com>
Wed, 4 Nov 2020 11:08:10 +0000 (11:08 +0000)
committerKerry McLaughlin <kerry.mclaughlin@arm.com>
Wed, 4 Nov 2020 11:38:49 +0000 (11:38 +0000)
commitf2412d372d93b8c9f6e08fd2166e1e161ba4e6f8
tree4cdf27fc4ef1756ee313658b7d3231acb92e6376
parentf202d32216c64b1ae8853a0506b85674cf52126a
[SVE][CodeGen] Lower scalable integer vector reductions

This patch uses the existing LowerFixedLengthReductionToSVE function to also lower
scalable vector reductions. A separate function has been added to lower VECREDUCE_AND
& VECREDUCE_OR operations with predicate types using ptest.

Lowering scalable floating-point reductions will be addressed in a follow up patch,
for now these will hit the assertion added to expandVecReduce() in TargetLowering.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D89382
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/test/CodeGen/AArch64/sve-int-pred-reduce.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/sve-int-reduce.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/sve-split-int-pred-reduce.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll