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(parent: b4e7657) | patch
[Arm64] Implement BitwiseSelect hardware intrinsic (#472)
authorEgor Chesakov <Egor.Chesakov@microsoft.com>
Thu, 5 Dec 2019 20:10:01 +0000 (12:10 -0800)
committerGitHub <noreply@github.com>
Thu, 5 Dec 2019 20:10:01 +0000 (12:10 -0800)
commitf2390f0ff562caaeaf1582e2d591a9893881fdc8
tree322222b459d4986b4268cd8d14d0ce9d6deecd19tree | snapshot
parentb4e7657f5d21c4ff2bd3860a4b4cc5d494aa6d8fcommit | diff
[Arm64] Implement BitwiseSelect hardware intrinsic (#472)
27 files changed:
src/coreclr/src/jit/codegen.h diff | blob | history
src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp diff | blob | history
src/coreclr/src/jit/hwintrinsiclistarm64.h diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_r.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_ro.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector128.Byte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector128.Double.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector128.Int16.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector128.Int32.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector128.Int64.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector128.SByte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector128.Single.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector128.UInt16.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector128.UInt32.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector128.UInt64.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector64.Byte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector64.Int16.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector64.Int32.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector64.SByte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector64.Single.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector64.UInt16.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/BitwiseSelect.Vector64.UInt32.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd.cs diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/GenerateTests.csx diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/_TernaryOpTestTemplate.template [new file with mode: 0644] blob
Domain: Dotnet / Core;