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[RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.
authorCraig Topper <craig.topper@sifive.com>
Thu, 24 Jun 2021 22:53:47 +0000 (15:53 -0700)
committerCraig Topper <craig.topper@sifive.com>
Fri, 25 Jun 2021 01:06:36 +0000 (18:06 -0700)
commitf225367305c82ce391bb470f735b19e924ff7372
tree8949c2a9e112a7705aa2f7b21a0e2e19109a1fd4tree | snapshot
parente8cded57fbf7b2b81aefd569b95f38ae97948ef0commit | diff
[RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.

These allow getting a whole register from a larger lmul. Or
inserting a whole register into a larger lmul register. Fractional
lmuls are not supported as they would require a vslide.

Based on this update to the intrinsic doc
https://github.com/riscv/rvv-intrinsic-doc/pull/99

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D104822
clang/include/clang/Basic/riscv_vector.td diff | blob | history
clang/lib/Sema/SemaChecking.cpp diff | blob | history
clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c [new file with mode: 0644] blob
clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c [new file with mode: 0644] blob
Domain: System / Toolchain;