perf/x86/intel: Add LBR filter support for Silvermont and Airmont CPUs
authorKan Liang <kan.liang@intel.com>
Fri, 15 Apr 2016 07:53:45 +0000 (00:53 -0700)
committerIngo Molnar <mingo@kernel.org>
Sat, 23 Apr 2016 12:12:31 +0000 (14:12 +0200)
commitf21d5adceb7f2660e5227569faed278f6fb2072e
tree3a69b653bffe6100bbb5a1063f6fa779d61dbf8f
parent8b92c3a78d40fb220dc5ab122e3274d1b126bfbb
perf/x86/intel: Add LBR filter support for Silvermont and Airmont CPUs

LBR filtering is also supported on the Silvermont and Airmont
microarchitectures. The layout of MSR_LBR_SELECT is the same as Nehalem.

Signed-off-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1460706825-46163-1-git-send-email-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/events/intel/core.c
arch/x86/events/intel/lbr.c
arch/x86/events/perf_event.h