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(parent: 6c18566) | patch
clk: renesas: r9a07g043: Add ethernet clock sources
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 2 Apr 2022 07:46:24 +0000 (08:46 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 13 Apr 2022 10:30:18 +0000 (12:30 +0200)
commitf201eb84450f98decb1834e73409bb2271441dd7
tree675474ea424415a2df8320754aa66ef832bc9641tree | snapshot
parent6c185664b3d481292c41fbfe66ea19c84cb0237acommit | diff
clk: renesas: r9a07g043: Add ethernet clock sources

Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add
support for ethernet source clock selection using SEL_PLL_6_2 mux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g043-cpg.c diff | blob | history
Domain: System / Kernel;