projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b97d8b3) | patch
[RISCV] Fix bugs in pseudo instructions for masked segment load.
authorHsiangkai Wang <kai.wang@sifive.com>
Thu, 18 Feb 2021 06:52:19 +0000 (14:52 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Thu, 18 Feb 2021 14:17:00 +0000 (22:17 +0800)
commitf1efa8abaf8e4fac5ef37aeb10d607ceecdb4ece
treee019b495ff309e111457d73ad3be1bfc2f4423d8tree | snapshot
parentb97d8b32c32bd38ab5f7aa75a25dc31a9564fdc2commit | diff
[RISCV] Fix bugs in pseudo instructions for masked segment load.

For masked segment load, the destination register should not overlap
with mask register. It could not be V0.

In the original implementation, there is no segment load/store register
class without V0. In this patch, I added these register classes and
modify `GetVRegNoV0` to get the correct one.

Differential Revision: https://reviews.llvm.org/D96937
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
llvm/lib/Target/RISCV/RISCVRegisterInfo.td diff | blob | history
Domain: System / Toolchain;