[X86] AVX512FP16 instructions enabling 2/6
authorWang, Pengfei <pengfei.wang@intel.com>
Sun, 15 Aug 2021 00:17:30 +0000 (08:17 +0800)
committerWang, Pengfei <pengfei.wang@intel.com>
Sun, 15 Aug 2021 00:56:33 +0000 (08:56 +0800)
commitf1de9d6dae174feb5000ad6a1b492b8cb717f5b6
tree3dff92d5993eae4d75604cca40381bc902f1073a
parent45138f788c9b3c4ac5d9ae4479841c411c15190e
[X86] AVX512FP16 instructions enabling 2/6

Enable FP16 binary operator instructions.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105264
47 files changed:
clang/include/clang/Basic/BuiltinsX86.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Headers/avx512fp16intrin.h
clang/lib/Headers/avx512vlfp16intrin.h
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/X86/avx512fp16-builtins.c
clang/test/CodeGen/X86/avx512vlfp16-builtins.c
llvm/include/llvm/IR/IntrinsicsX86.td
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrFoldTables.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86IntrinsicsInfo.h
llvm/test/CodeGen/X86/avx512fp16-arith-intrinsics.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/avx512fp16-arith-vl-intrinsics.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/avx512fp16-arith.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/avx512fp16-fmaxnum.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/avx512fp16-fminnum.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/avx512fp16-fold-load-binops.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/avx512fp16-fold-xmm-zero.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/avx512fp16-machine-combiner.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/avx512fp16-mov.ll
llvm/test/CodeGen/X86/avx512fp16-unsafe-fp-math.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/fp-strict-scalar-fp16.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/pseudo_cmov_lower-fp16.ll
llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/vec-strict-128-fp16.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/vec-strict-256-fp16.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/vec-strict-512-fp16.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/vec-strict-cmp-128-fp16.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/vec-strict-cmp-256-fp16.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/vec-strict-cmp-512-fp16.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
llvm/test/MC/Disassembler/X86/avx512fp16.txt
llvm/test/MC/Disassembler/X86/avx512fp16vl.txt [new file with mode: 0644]
llvm/test/MC/X86/avx512fp16.s
llvm/test/MC/X86/avx512fp16vl.s [new file with mode: 0644]
llvm/test/MC/X86/intel-syntax-avx512fp16.s
llvm/test/MC/X86/intel-syntax-avx512fp16vl.s [new file with mode: 0644]