projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: bf6d7ca) | patch
[SDAG] neg x with only low bit demanded is x
authorPhilip Reames <preames@rivosinc.com>
Mon, 19 Dec 2022 23:24:45 +0000 (15:24 -0800)
committerPhilip Reames <listmail@philipreames.com>
Mon, 19 Dec 2022 23:25:43 +0000 (15:25 -0800)
commitf1dcb9c36fe46c97a8f22c8b2544fb25d2e4cb61
treee466ec4d7ae58c667d8b68153254777ded5e9eddtree | snapshot
parentbf6d7ca9870beb66766e2c087f5109eeb538f530commit | diff
[SDAG] neg x with only low bit demanded is x

We have a version of this transform in InstCombine, but surprisingly not in SDAG.  Even more surprisingly, this benefits RISCV, but no other target. This was surprising enough I double checked my build configuration to make sure all targets were enabled; they appear to be.

Differential Revision: https://reviews.llvm.org/D140324
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff | blob | history
llvm/test/CodeGen/RISCV/alu64.ll diff | blob | history
llvm/test/CodeGen/RISCV/bittest.ll diff | blob | history
llvm/test/CodeGen/RISCV/forced-atomics.ll diff | blob | history
llvm/test/CodeGen/RISCV/fpclamptosat.ll diff | blob | history
Domain: System / Toolchain;