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(parent: d238100) | patch
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
authorXingyu Wu <xingyu.wu@starfivetech.com>
Thu, 16 Mar 2023 03:05:12 +0000 (11:05 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Mon, 24 Jul 2023 23:24:36 +0000 (08:24 +0900)
commitf1ce6e1da08186087bfa321461c2a02e7352a997
tree1ebe50bbea0865f458c644732a2eaafb286b2aadtree | snapshot
parentd238100d11c33b13412bd1fdef07282efdd59d8ecommit | diff
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs

Add PLL clock inputs from PLL clock generator.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml diff | blob | history
Domain: System / Kernel;