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[X86] Add test case showing incorrect and(sextinreg(v0,i2),sextinreg(v1,i5)) -> sexti...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 20 Jul 2023 09:25:40 +0000 (10:25 +0100)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 20 Jul 2023 09:44:46 +0000 (10:44 +0100)
commitf1cc7913f3bfbb288ef44645a432aeac80dbf139
tree6689c35322590b797974ea3ccb98830c3eb7be65tree | snapshot
parent2e0bf67df1437cb0156d7f5dd9e1b701749f96cacommit | diff
[X86] Add test case showing incorrect and(sextinreg(v0,i2),sextinreg(v1,i5)) -> sextinreg(and(v0,v1),i2) fold
llvm/test/CodeGen/X86/scalar-ext-logic.ll [new file with mode: 0644] blob
Domain: System / Toolchain;