clk: rockchip: add clock controller for the RK3588
authorElaine Zhang <zhangqing@rock-chips.com>
Tue, 18 Oct 2022 15:14:07 +0000 (17:14 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 15 Nov 2022 10:37:41 +0000 (11:37 +0100)
commitf1c506d152ff235ad621d3c25d061cb16da67214
tree62f295cf3fcb13706e78dbcf0a6295893b03a649
parentada8f95ba04e8fe07289b7de157ae99bb96bc8cb
clk: rockchip: add clock controller for the RK3588

Add full clock controller support RK3588.

[rebase, integrate fixes from Wyon and Finley, add missing frequencies
 to PLL lookup table, update commit message, add GATE_LINK clocks which
 downstream handles in its own driver with one DT node per clock]

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com
[dropped module stuff after talking to Sebastian]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/Kconfig
drivers/clk/rockchip/Makefile
drivers/clk/rockchip/clk-rk3588.c [new file with mode: 0644]
drivers/clk/rockchip/clk.h
drivers/clk/rockchip/rst-rk3588.c [new file with mode: 0644]