MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it
authorMatthias Braun <matze@braunis.de>
Wed, 24 Aug 2016 22:17:45 +0000 (22:17 +0000)
committerMatthias Braun <matze@braunis.de>
Wed, 24 Aug 2016 22:17:45 +0000 (22:17 +0000)
commitf1b20c52251af54413ca5b990db2b29d9418e256
tree96d10ad56be92728945892ae5f53b5ca9113f18f
parentf17227a1da6fca7d89fd072410784ff35154e2e5
MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it

tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there
is not need to change it or save/parse it in a .mir file.
Make the field const and move the initialization LiveIntervalAnalysis to the
MachineRegisterInfo constructor. Also cleanup some code and fix some
instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead
of TargetSubtargetInfo::enableSubRegLiveness().

llvm-svn: 279676
26 files changed:
llvm/include/llvm/CodeGen/MIRYamlMapping.h
llvm/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/include/llvm/Target/TargetSubtargetInfo.h
llvm/lib/CodeGen/DetectDeadLanes.cpp
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineRegisterInfo.cpp
llvm/lib/CodeGen/RenameIndependentSubregs.cpp
llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
llvm/test/CodeGen/AArch64/movimm-wzr.mir
llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir
llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
llvm/test/CodeGen/MIR/Generic/register-info.mir
llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir
llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
llvm/test/CodeGen/X86/implicit-null-checks.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values.mir