pinctrl: aspeed-g5: Add mux configuration for all pins
authorAndrew Jeffery <andrew@aj.id.au>
Tue, 20 Dec 2016 07:35:50 +0000 (18:05 +1030)
committerLinus Walleij <linus.walleij@linaro.org>
Wed, 28 Dec 2016 00:21:23 +0000 (01:21 +0100)
commitf1337856dd88858bf58bd062306ccbfb63303085
tree9dc436fd27bbc6e73caf8372327561c225eb5d88
parent6d329f14a75f3858a1254abca8b94d4fab556a9a
pinctrl: aspeed-g5: Add mux configuration for all pins

The patch introducing the g5 pinctrl driver implemented a smattering of
pins to flesh out the implementation of the core and provide bare-bones
support for some OpenPOWER platforms and the AST2500 evaluation board.
Now, update the bindings document to reflect the complete functionality
and implement the necessary pin configuration tables in the driver.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
drivers/pinctrl/aspeed/pinctrl-aspeed.h