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(parent: 67cfbcc) | patch
dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
authorXingyu Wu <xingyu.wu@starfivetech.com>
Tue, 14 Mar 2023 12:44:00 +0000 (20:44 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Mon, 24 Jul 2023 23:24:35 +0000 (08:24 +0900)
commitf120adf23c83fb81ea69ff884c49fce43a6fe2dd
tree15d2f273f44741349d883bfcf05f1261533992e7tree | snapshot
parent67cfbccec5a7b4a064db9a777903a64e17edc903commit | diff
dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator

Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml [new file with mode: 0644] blob
include/dt-bindings/clock/starfive,jh7110-crg.h diff | blob | history
include/dt-bindings/reset/starfive,jh7110-crg.h diff | blob | history
Domain: System / Kernel;