[mips] Preparatory work for a generic scheduler
authorSimon Dardis <simon.dardis@imgtec.com>
Wed, 24 Aug 2016 13:00:47 +0000 (13:00 +0000)
committerSimon Dardis <simon.dardis@imgtec.com>
Wed, 24 Aug 2016 13:00:47 +0000 (13:00 +0000)
commitf114820912b8484a9b40429dd58dd829a87d8c58
treebe69ca39d7d8c08ea7eeefffca70969016558f84
parent7a50c8c2ba58beaa70879d22c628ebd213fcf4ee
[mips] Preparatory work for a generic scheduler

Extend instruction definitions from nearly all ISAs to include
appropriate instruction itineraries. Change MIPS16s gp prologue
generation to use real instructions instead of using a pseudo
instruction.

Reviewers: dsanders, vkalintiris

Differential Review: https://reviews.llvm.org/D23548

llvm-svn: 279623
23 files changed:
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
llvm/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/lib/Target/Mips/Mips64InstrInfo.td
llvm/lib/Target/Mips/Mips64r6InstrInfo.td
llvm/lib/Target/Mips/MipsSchedule.td
llvm/test/CodeGen/Mips/llvm-ir/add.ll
llvm/test/CodeGen/Mips/llvm-ir/and.ll
llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
llvm/test/CodeGen/Mips/llvm-ir/mul.ll
llvm/test/CodeGen/Mips/llvm-ir/not.ll
llvm/test/CodeGen/Mips/llvm-ir/or.ll
llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
llvm/test/CodeGen/Mips/llvm-ir/shl.ll
llvm/test/CodeGen/Mips/llvm-ir/srem.ll
llvm/test/CodeGen/Mips/llvm-ir/sub.ll
llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
llvm/test/CodeGen/Mips/llvm-ir/urem.ll
llvm/test/CodeGen/Mips/llvm-ir/xor.ll