RISC-V: Avoid using per cpu array for ordered booting

RISC-V: Avoid using per cpu array for ordered booting

Currently both order booting and spinwait approach uses a per cpu
array to update stack & task pointer. This approach will not work for the
following cases.
1. If NR_CPUs are configured to be less than highest hart id.
2. A platform has sparse hartid.

This issue can be fixed for ordered booting as the booting cpu brings up
one cpu at a time using SBI HSM extension which has opaque parameter
that is unused until now.

Introduce a common secondary boot data structure that can store the stack
and task pointer. Secondary harts will use this data while booting up
to setup the sp & tp.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
From 9a2451f1866344d38b4a1dc20396e3a03954fcd7
Resolved merge conflict.

Signed-off-by: <jeeheng.sia@starfivetech.com>
Signed-off-by: minda.chen <minda.chen@starfivetech.com>