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(parent: c7e7815) | patch
[RISCV] Add fcvt.s.w(u)/fcvt.d.w(u)/fcvt.h.w(u) to hasAllNBitUsers
authorCraig Topper <craig.topper@sifive.com>
Wed, 22 Sep 2021 21:21:03 +0000 (14:21 -0700)
committerCraig Topper <craig.topper@sifive.com>
Wed, 22 Sep 2021 21:24:26 +0000 (14:24 -0700)
commitf0a422f935af877d8d9304eacbfbb6621e9ff643
treefebc1f147feeede99f14ed99c0b646ed1ab7b42ftree | snapshot
parentc7e78150f733d5be3cae766de3385173e2e245ffcommit | diff
[RISCV] Add fcvt.s.w(u)/fcvt.d.w(u)/fcvt.h.w(u) to hasAllNBitUsers

These instructions only read the lower 32 bits of their input.
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/RISCV/double-convert.ll diff | blob | history
llvm/test/CodeGen/RISCV/float-convert.ll diff | blob | history
llvm/test/CodeGen/RISCV/half-convert.ll diff | blob | history
Domain: System / Toolchain;