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(parent: c349b41) | patch
net/mlx5: DR, Use the right size when writing partial STE into HW
authorYevgeny Kliteynik <kliteyn@nvidia.com>
Tue, 22 Sep 2020 01:23:58 +0000 (04:23 +0300)
committerSaeed Mahameed <saeedm@nvidia.com>
Sat, 30 Jan 2021 02:12:52 +0000 (18:12 -0800)
commitf06d496985f49189dde4506d0ac15494d1a74607
treec318012e6de56d8caf0dbff0914bb08c6c02b259tree | snapshot
parentc349b4137cfd9482f30dcd726748d0c4da1427f3commit | diff
net/mlx5: DR, Use the right size when writing partial STE into HW

In these cases we need to update only the ctrl area of the STE.
So it is better to write only the control 32B and avoid copying
the unneeded reduced 48B (control 32B + tag 16B).

Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c diff | blob | history
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c diff | blob | history
Domain: System / Kernel;