drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits
authorChris Wilson <chris@chris-wilson.co.uk>
Sun, 20 Jan 2013 16:33:32 +0000 (16:33 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 22 Jan 2013 23:58:23 +0000 (00:58 +0100)
commitf05bb0c7b624252a5e768287e340e8e45df96e42
tree4824aaa30158b81aff2cea25eaaf29dbb411a550
parent1c8c38c588ea91f8deeae21284840459d1bb58e3
drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits

On SNB, if bit 13 of GFX_MODE, Flush TLB Invalidate Mode, is not set to 1,
the hardware can not program the scanline values. Those scanline values
then control when the signal is sent from the display engine to the render
ring for MI_WAIT_FOR_EVENTs. Note setting this bit means that TLB
invalidations must be performed explicitly through the appropriate bits
being set in PIPE_CONTROL.

References: https://bugzilla.kernel.org/show_bug.cgi?id=52311
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@vger.kernel.org
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ringbuffer.c