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Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"
authorMika Kuoppala <mika.kuoppala@linux.intel.com>
Wed, 6 May 2020 14:47:31 +0000 (17:47 +0300)
committerChris Wilson <chris@chris-wilson.co.uk>
Thu, 7 May 2020 06:44:40 +0000 (07:44 +0100)
commitf02ac414ba9497d1887b1de7fe69954284f157ac
tree8c26324826f1e9eecb0f3cd6218e444a2f02da4etree | snapshot
parent24fe5f2ab2478053d50a3bc629ada895903a5cbccommit | diff
Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

This reverts commit 62037ffff229b7d94f1db5ef8d2e2ec819832ef3.

L3 ro cache invalidation is part of the dword0 of pipe
control. Also it is not relevant to this gen.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200506144734.29297-1-mika.kuoppala@linux.intel.com
drivers/gpu/drm/i915/gt/intel_gpu_commands.h diff | blob | history
drivers/gpu/drm/i915/gt/intel_lrc.c diff | blob | history
Domain: System / Kernel;