i965/fs: Don't follow pow with an instruction with two dest regs.
authorMatt Turner <mattst88@gmail.com>
Tue, 3 May 2016 06:32:13 +0000 (23:32 -0700)
committerMatt Turner <mattst88@gmail.com>
Thu, 5 May 2016 17:18:28 +0000 (10:18 -0700)
commitf01d92f4734a7ca62926dceda1d004c0cb10548c
treef5c3ac8ddaccf61de72f36a227ad60a22bb77c8c
parent9d86a5eea79ac30bb90af363c66a5ba8529b37d8
i965/fs: Don't follow pow with an instruction with two dest regs.

Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on
Gen >= 8 platforms.

Evidently that commit allowed the scheduler to make different choices
that somehow finally ran afoul of a hardware bug in which POW and FDIV
instructions may not be followed by an instruction with two destination
registers (including compressed instructions). I presume the conditions
are more complex than that, but the internal hardware bug report (BDWGFX
bug_de 1696294) does not contain much more information.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94924
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> [v1]
Tested-by: Mark Janes <mark.a.janes@intel.com> [v1]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
src/mesa/drivers/dri/i965/brw_fs_generator.cpp