RISC-V: Introduce a new config for SBI v0.1
authorAtish Patra <atish.patra@wdc.com>
Wed, 18 Mar 2020 01:11:37 +0000 (18:11 -0700)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Tue, 31 Mar 2020 18:25:40 +0000 (11:25 -0700)
commitefca13989250c3edebaf8fcaa8ca7c966739c65a
tree6fa5dd8ceffcbbeec9d8b9542a27949d8b7a0ce4
parentecbacc2a3efd90cae34790379cc3e1b4932889d0
RISC-V: Introduce a new config for SBI v0.1

We now have SBI v0.2 which is more scalable and extendable to handle
future needs for RISC-V supervisor interfaces.

Introduce a new config and move all SBI v0.1 code under that config.
This allows to implement the new replacement SBI extensions cleanly
and remove v0.1 extensions easily in future. Currently, the config
is enabled by default. Once all M-mode software, with v0.1, is no
longer in use, this config option and all relevant code can be easily
removed.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
arch/riscv/Kconfig
arch/riscv/include/asm/sbi.h
arch/riscv/kernel/sbi.c