clk: tegra20: Correct parents of CDEV1/2 clocks
authorDmitry Osipenko <digetx@gmail.com>
Tue, 8 May 2018 16:26:05 +0000 (19:26 +0300)
committerThierry Reding <treding@nvidia.com>
Fri, 18 May 2018 10:35:07 +0000 (12:35 +0200)
commitefc351b1f46f55ba3f9fa83c490c55243c3a676b
tree621b706c8b45dd7c5aad6af59ebc50ab3539b8bb
parent08a52593fc0dca4b798f9a222cfbc827d008c1bf
clk: tegra20: Correct parents of CDEV1/2 clocks

Parents of CDEV1/2 clocks are determined by muxing of the corresponding
pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence
CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the
corresponding muxes to fix the parents.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra20.c