clk: samsung: exynos4: Register PLL rate tables for Exynos4x12
authorTomasz Figa <t.figa@samsung.com>
Mon, 26 Aug 2013 17:09:10 +0000 (19:09 +0200)
committerMike Turquette <mturquette@linaro.org>
Fri, 6 Sep 2013 20:34:01 +0000 (13:34 -0700)
commitefb19a85cb0b44c06ed5ff7c397341ab852148e5
tree8d16afce3f44f1d79057726bcfb5c4af99d82edd
parent5fadfc7ed37efe272983639f0d2f8c801303e796
clk: samsung: exynos4: Register PLL rate tables for Exynos4x12

This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4x12 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/samsung/clk-exynos4.c