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(parent: 82952de) | patch
anv: Add ANV_PIPE_HDC_PIPELINE_FLUSH_BIT
authorFelix DeGrood <felix.j.degrood@intel.com>
Thu, 18 Mar 2021 02:46:41 +0000 (19:46 -0700)
committerMarge Bot <eric+marge@anholt.net>
Tue, 15 Jun 2021 12:57:42 +0000 (12:57 +0000)
commitef70388a3a183e83ab4a8fb059c83587de295cea
tree8efec81ffd66b8eaa23a6a98d7be302b871f9bb1tree | snapshot
parent82952deb8b80ff705586f1e4f3b98dee463cd09bcommit | diff
anv: Add ANV_PIPE_HDC_PIPELINE_FLUSH_BIT

Gfx12+ PIPE_CONTROL bit for flushing HDC cache and memory
transactions to L3 cache.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
src/intel/vulkan/anv_private.h diff | blob | history
src/intel/vulkan/anv_util.c diff | blob | history
src/intel/vulkan/genX_cmd_buffer.c diff | blob | history
Domain: Graphics System / GL;