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(parent: cdae0a4) | patch
MIR Serialization: Serialize the target index machine operands.
authorAlex Lorenz <arphaman@gmail.com>
Tue, 28 Jul 2015 23:02:45 +0000 (23:02 +0000)
committerAlex Lorenz <arphaman@gmail.com>
Tue, 28 Jul 2015 23:02:45 +0000 (23:02 +0000)
commitef5c196fb04820c808b70288d58a9eca423091b1
treecf92406cdb57f9c46f9f3c8441d86a9a07e92628tree | snapshot
parentcdae0a4e2d2a3d6755762bfee63467ab7f192069commit | diff
MIR Serialization: Serialize the target index machine operands.

Reviewers: Duncan P. N. Exon Smith
llvm-svn: 243497
llvm/include/llvm/Target/TargetInstrInfo.h diff | blob | history
llvm/lib/CodeGen/MIRParser/MILexer.cpp diff | blob | history
llvm/lib/CodeGen/MIRParser/MILexer.h diff | blob | history
llvm/lib/CodeGen/MIRParser/MIParser.cpp diff | blob | history
llvm/lib/CodeGen/MIRPrinter.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h diff | blob | history
llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir [new file with mode: 0644] blob
llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir [new file with mode: 0644] blob
llvm/test/CodeGen/MIR/AMDGPU/lit.local.cfg [new file with mode: 0644] blob
llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir [new file with mode: 0644] blob
Domain: System / Toolchain;