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(parent: 0608e76) | patch
intel/compiler: Handle ternary add in lower_simd_width
authorSagar Ghuge <sagar.ghuge@intel.com>
Wed, 21 Jul 2021 22:24:29 +0000 (15:24 -0700)
committerMarge Bot <eric+marge@anholt.net>
Thu, 22 Jul 2021 23:38:04 +0000 (23:38 +0000)
commitef29bb6bc53bf07097ddaf6329c8892f50168e7e
tree174047130a73047fd368d4fc62360fec85a2f9f6tree | snapshot
parent0608e76e00da8921be1532340f8448215e8438b6commit | diff
intel/compiler: Handle ternary add in lower_simd_width

We need to lower the add3 instruction simd width otherwise in simd32
mode, we endup writing 4 register wide data which is not allowed.

Reported-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11985>
src/intel/compiler/brw_fs.cpp diff | blob | history
Domain: Graphics System / GL;