clk: renesas: Add r8a774e1 CPG Core Clock Definitions
authorMarian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Tue, 7 Jul 2020 16:18:09 +0000 (17:18 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 13 Jul 2020 08:18:05 +0000 (10:18 +0200)
commitef1c9924287d11660cfc7900aeeeb4732188743e
tree9cdcec74f13c495b73cabb292df8afe625d92cbc
parente24779649c840ce1ecb638a30e7c821075630184
clk: renesas: Add r8a774e1 CPG Core Clock Definitions

Add all RZ/G2H Clock Pulse Generator Core Clock Outputs, as listed in
Table 11.2 ("List of Clocks [RZ/G2H]") of the RZ/G2H Hardware User's
Manual.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594138692-16816-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
include/dt-bindings/clock/r8a774e1-cpg-mssr.h [new file with mode: 0644]