riscv: dts: starfive: Add JH7100 CPU topology
authorJonas Hahnfeld <hahnjo@hahnjo.de>
Tue, 5 Jul 2022 19:04:32 +0000 (20:04 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 14 Jul 2022 21:37:00 +0000 (14:37 -0700)
commitef09fa67dc7dc7d839d8f9bee43ecacc83401de5
treef6eb04d1a628d68c39170debcc1930702971465a
parentf2906aa863381afb0015a9eb7fefad885d4e5a56
riscv: dts: starfive: Add JH7100 CPU topology

Add cpu-map binding to inform the kernel about the hardware topology
of the CPU cores.

Before this change, lstopo would report 1 core with 2 threads:
Machine (7231MB total)
  Package L#0
    NUMANode L#0 (P#0 7231MB)
    L2 L#0 (2048KB) + Core L#0
      L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0)
      L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1)

After this change, it correctly identifies two cores:
Machine (7231MB total)
  Package L#0
    NUMANode L#0 (P#0 7231MB)
    L2 L#0 (2048KB)
      L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
      L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)

Signed-off-by: Jonas Hahnfeld <hahnjo@hahnjo.de>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220705190435.1790466-2-mail@conchuod.ie
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/boot/dts/starfive/jh7100.dtsi