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(parent: 5d361ad) | patch
IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 27 Apr 2023 02:02:42 +0000 (22:02 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 6 Jun 2023 21:07:18 +0000 (17:07 -0400)
commiteece6ba283bd763e6d7109ae9e155e81cfee0651
tree854043bb8788f9ea3199c9f506d12e40cc9c6ea0tree | snapshot
parent5d361ad2a4d41edcc796aa83c0dbf9420ca4929fcommit | diff
IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics

AMDGPU has native instructions and target intrinsics for this, but
these really should be subject to legalization and generic
optimizations. This will enable legalization of f16->f32 on targets
without f16 support.

Implement a somewhat horrible inline expansion for targets without
libcall support. This could be better if we could introduce control
flow (GlobalISel version not yet implemented). Support for strictfp
legalization is less complete but works for the simple cases.
71 files changed:
clang/lib/CodeGen/CGBuiltin.cpp diff | blob | history
clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl diff | blob | history
clang/test/CodeGenOpenCL/builtins-amdgcn.cl diff | blob | history
llvm/docs/LangRef.rst diff | blob | history
llvm/docs/ReleaseNotes.rst diff | blob | history
llvm/include/llvm/Analysis/TargetLibraryInfo.h diff | blob | history
llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h diff | blob | history
llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h diff | blob | history
llvm/include/llvm/CodeGen/ISDOpcodes.h diff | blob | history
llvm/include/llvm/CodeGen/RuntimeLibcalls.h diff | blob | history
llvm/include/llvm/IR/ConstrainedOps.def diff | blob | history
llvm/include/llvm/IR/Intrinsics.td diff | blob | history
llvm/include/llvm/IR/RuntimeLibcalls.def diff | blob | history
llvm/include/llvm/Support/TargetOpcodes.def diff | blob | history
llvm/include/llvm/Target/GenericOpcodes.td diff | blob | history
llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td diff | blob | history
llvm/include/llvm/Target/TargetSelectionDAG.td diff | blob | history
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp diff | blob | history
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h diff | blob | history
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp diff | blob | history
llvm/lib/CodeGen/TargetLoweringBase.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIISelLowering.h diff | blob | history
llvm/lib/Target/AMDGPU/VOP2Instructions.td diff | blob | history
llvm/lib/Target/AMDGPU/VOP3Instructions.td diff | blob | history
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff | blob | history
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir [deleted file] blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir [deleted file] blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.f16.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/Mips/ldexp.ll [new file with mode: 0644] blob
llvm/test/CodeGen/PowerPC/ldexp-libcall.ll [new file with mode: 0644] blob
llvm/test/CodeGen/PowerPC/ldexp.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/ldexp-f80.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/ldexp-libcall.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/ldexp-not-readonly.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/ldexp-strict.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/ldexp-wrong-signature.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/ldexp-wrong-signature2.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/ldexp.ll [new file with mode: 0644] blob
llvm/test/MC/AMDGPU/gfx10_asm_vop2.s diff | blob | history
llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s diff | blob | history
llvm/test/MC/AMDGPU/gfx8_asm_vop3.s diff | blob | history
llvm/test/MC/AMDGPU/gfx9_asm_vop3.s diff | blob | history
llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3.txt diff | blob | history
llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop2.txt diff | blob | history
llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt diff | blob | history
llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt diff | blob | history
llvm/test/Transforms/SpeculativeExecution/spec-calls.ll diff | blob | history
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