Recommit "[SelectionDAG][RISCV] Add very basic PromoteIntegerResult/Op support for...
authorCraig Topper <craig.topper@sifive.com>
Thu, 15 Jun 2023 19:03:25 +0000 (12:03 -0700)
committerCraig Topper <craig.topper@sifive.com>
Thu, 15 Jun 2023 19:03:25 +0000 (12:03 -0700)
commiteea865bd4a5348da374586d156aa1cc92eaeb562
treeff76c93c8026fe8eed2601eb9a23f4926f69763e
parentf03a16e633f2ca67e6e1100955e223c64c76dc71
Recommit "[SelectionDAG][RISCV] Add very basic PromoteIntegerResult/Op support for VP_SIGN/ZERO_EXTEND."

I have fixed an existing DAGCombiner bug that caused the previous assertion failure.
See 7163539466d7e8930416e55dd9fd29891f8239f2.

Original message

We don't have VP_ANY_EXTEND or VP_SIGN_EXTEND_INREG yet so I've
deviated a little from the non-VP lowering.

My goal was to fix the crashes that occurs on these test cases without this patch.

Reviewed By: fakepaper56

Differential Revision: https://reviews.llvm.org/D152854
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll