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(parent: c325916) | patch
MIPS: mips32/cache.S: store cache line size in t8 register
authorGabor Juhos <juhosg@openwrt.org>
Thu, 13 Jun 2013 10:59:35 +0000 (12:59 +0200)
committerTom Rini <trini@ti.com>
Wed, 24 Jul 2013 13:51:07 +0000 (09:51 -0400)
commitee8b1e29597bcf18bfebd6fd8eccc8e245046352
tree0bc3e953a2bf45c34e985dd7a8714a674c3ce440tree | snapshot
parentc325916563ac67ec5f86748060c2909a9b960beecommit | diff
MIPS: mips32/cache.S: store cache line size in t8 register

Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
arch/mips/cpu/mips32/cache.S diff | blob | history
Domain: System / Kernel;