microblaze: exception: fix return address for delay slot exceptions
authorOvidiu Panait <ovidiu.panait@windriver.com>
Sun, 13 Feb 2022 08:09:22 +0000 (10:09 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 15 Feb 2022 12:11:43 +0000 (13:11 +0100)
commitee8161f7d182e57ea828f77a6b246c884c70b7cd
treeaeee6ced6a02ba6d2f266cdaf102d9b7db4758d7
parent7422b411757faa2a01487b43138f29b4fdde3c74
microblaze: exception: fix return address for delay slot exceptions

According to the MicroBlaze reference manual (xilinx2021.2/ug984/page-37):
"""
If an exception is caused by an instruction in a delay slot (that is,
ESR[DS]=1), the exception handler should return execution to
the address stored in BTR instead of the normal exception return
address stored in R17.
"""

Adjust the code to print the proper return address for delay slot
exceptions.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-4-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/microblaze/cpu/exception.c