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(parent: 08f8d04) | patch
cxl/port: Cache CXL host bridge data
authorDan Williams <dan.j.williams@intel.com>
Wed, 1 Jun 2022 19:49:32 +0000 (12:49 -0700)
committerDan Williams <dan.j.williams@intel.com>
Sun, 10 Jul 2022 19:10:07 +0000 (12:10 -0700)
commitee800010835db23c70acc01000f182955cab27a5
treebb7678bc2cd22ea26b50b23f772d1124de3e61d9tree | snapshot
parent08f8d040a11d539481b9aee7b482430561281a28commit | diff
cxl/port: Cache CXL host bridge data

Region creation has need for checking host-bridge connectivity when
adding endpoints to regions. Record, at port creation time, the
host-bridge to provide a useful shortcut from any location in the
topology to the most-significant ancestor.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20220624041950.559155-4-dan.j.williams@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/core/port.c diff | blob | history
drivers/cxl/cxl.h diff | blob | history
Domain: System / Kernel;