projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: a406605) | patch
MIR: Infer not-SSA for subregister defs
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Sun, 28 Jun 2020 15:34:42 +0000 (11:34 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 27 Aug 2020 20:56:16 +0000 (16:56 -0400)
commitee679638d75ca9a7f7d7be728fa069606dcc8ec7
tree3a2ed1fe9bbe991caf3d5693c987db016d84d7batree | snapshot
parenta40660551ea1ed01f69406d81e39efe73d86cbeccommit | diff
MIR: Infer not-SSA for subregister defs

It's possible to have a single virtual register def with a subreg
index that would pass the previous check, but it's not possible to
have a subregister def in SSA.

This is in preparation for adding stricter checks for SSA MIR.
llvm/include/llvm/CodeGen/MachineRegisterInfo.h diff | blob | history
llvm/lib/CodeGen/MIRParser/MIRParser.cpp diff | blob | history
llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir [new file with mode: 0644] blob
Domain: System / Toolchain;