irqchip: or1k-pic: Undefine mask_ack for level triggered hardware
authorStafford Horne <shorne@gmail.com>
Tue, 14 Jun 2022 23:54:26 +0000 (08:54 +0900)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 21 Jul 2022 19:24:40 +0000 (21:24 +0200)
commitee1da3d59674a1f6134fbe3dea7070e32f161083
treea2f1153db64e29a507193ebf38da7fd34c196547
parent9c9869c308a311ba7b5a48e6cdb3df22d63d088a
irqchip: or1k-pic: Undefine mask_ack for level triggered hardware

[ Upstream commit 8520501346ed8d1c4a6dfa751cb57328a9c843f1 ]

The mask_ack operation clears the interrupt by writing to the PICSR
register.  This we don't want for level triggered interrupt because
it does not actually clear the interrupt on the source hardware.

This was causing issues in qemu with multi core setups where
interrupts would continue to fire even though they had been cleared in
PICSR.

Just remove the mask_ack operation.

Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/irqchip/irq-or1k-pic.c