perf/x86/intel/uncore: Reduce the number of CBOX counters
authorKan Liang <kan.liang@linux.intel.com>
Fri, 25 Sep 2020 13:49:05 +0000 (06:49 -0700)
committerPeter Zijlstra <peterz@infradead.org>
Tue, 29 Sep 2020 07:57:01 +0000 (09:57 +0200)
commitee139385432e919f4d1f59b80edbc073cdae1391
tree6e21a42c78d0599ff8615cb889e1f0b9676b138c
parent8f5d41f3a0f495435c88ebba8fc150c931c10fef
perf/x86/intel/uncore: Reduce the number of CBOX counters

An oops is triggered by the fuzzy test.

[  327.853081] unchecked MSR access error: RDMSR from 0x70c at rIP:
0xffffffffc082c820 (uncore_msr_read_counter+0x10/0x50 [intel_uncore])
[  327.853083] Call Trace:
[  327.853085]  <IRQ>
[  327.853089]  uncore_pmu_event_start+0x85/0x170 [intel_uncore]
[  327.853093]  uncore_pmu_event_add+0x1a4/0x410 [intel_uncore]
[  327.853097]  ? event_sched_in.isra.118+0xca/0x240

There are 2 GP counters for each CBOX, but the current code claims 4
counters. Accessing the invalid registers triggers the oops.

Fixes: 6e394376ee89 ("perf/x86/intel/uncore: Add Intel Icelake uncore support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200925134905.8839-3-kan.liang@linux.intel.com
arch/x86/events/intel/uncore_snb.c