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Reorder (shl (add/sub (shl x, C0), y), C1) -> (add/sub (shl x, C0 + C1), (shl y,...
authorNoah Goldstein <goldstein.w.n@gmail.com>
Fri, 27 Jan 2023 23:26:41 +0000 (17:26 -0600)
committerNoah Goldstein <goldstein.w.n@gmail.com>
Fri, 27 Jan 2023 23:45:36 +0000 (17:45 -0600)
commitedd80befeeb92000800ded2a6f3dcdfd672d95ea
treebe24276d96cecf0c92d9a39ede3941091d5ad34dtree | snapshot
parent8c884655862ed2e4ca0f00de349387db77294c8bcommit | diff
Reorder (shl (add/sub (shl x, C0), y), C1) -> (add/sub (shl x, C0 + C1), (shl y, C1))

This is just expanding the existing pattern that exists for AND/XOR/OR
and gets a bit more parallelism in from the instruction sequence.

Alive2:
Add  - https://alive2.llvm.org/ce/z/dSmPkV
Sub1 - https://alive2.llvm.org/ce/z/6rpi5V
Sub2 - https://alive2.llvm.org/ce/z/UfYeUd

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D141875
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp diff | blob | history
llvm/test/Transforms/InstCombine/shift-logic.ll diff | blob | history
Domain: System / Toolchain;