[VPlan] Only generate single instr for stores uniform across all parts.
authorPhilip Reames <preames@rivosinc.com>
Fri, 9 Sep 2022 14:14:19 +0000 (07:14 -0700)
committerPhilip Reames <listmail@philipreames.com>
Fri, 9 Sep 2022 14:15:12 +0000 (07:15 -0700)
commitedb26268ce6e915377086fa1a3733254f64aeda3
tree2e350152409d1cafdab8a076375de599cb88e965
parentebbac868b54ecd109a9e440460136fe33df8a4ee
[VPlan] Only generate single instr for stores uniform across all parts.

Extend the approach taken by D133019 to store instructions.

Differential Revision: https://reviews.llvm.org/D133497
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll