[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
authorCraig Topper <craig.topper@sifive.com>
Wed, 25 Nov 2020 23:07:34 +0000 (15:07 -0800)
committerCraig Topper <craig.topper@sifive.com>
Wed, 25 Nov 2020 23:07:34 +0000 (15:07 -0800)
commited95cafbc5fa9efbfe3f38da0b17efdb3806598c
tree2989028923c57dd4aab18f5a494c8951e0a7df26
parent2d6042937b04eef00672b5c4ce623bf8f7b9a201
[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd

Start with an assumption that FMA is faster than Fmul+FAdd. If thats not true
on some particular implementation we can add a tuning parameter in the future.

I've update the fmuladd test cases and added new test cases for fast math flag
based contraction.

Differential Revision: https://reviews.llvm.org/D91987
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/test/CodeGen/RISCV/double-arith.ll
llvm/test/CodeGen/RISCV/double-intrinsics.ll
llvm/test/CodeGen/RISCV/float-arith.ll
llvm/test/CodeGen/RISCV/float-intrinsics.ll