drm/i915: Address broxton phy registers based on phy and channel number
authorAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Wed, 19 Oct 2016 07:59:00 +0000 (10:59 +0300)
committerAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Fri, 28 Oct 2016 09:25:24 +0000 (12:25 +0300)
commited37892e6df2a3caae4928583c211970a46375a6
treebae9efff3b9c8d87ac17b59266c37afc074f1762
parente7583f7b1018a862b2c93fd50650181881b2a0e1
drm/i915: Address broxton phy registers based on phy and channel number

The port registers related to the phys in broxton map to different
channels and specific phys. Make that mapping explicit.

v2: Pass enum dpio_phy to macros instead of mmio base. (Imre)

v3: Fix typo in macros. (Imre)

v4: Also change variables from u32 to enum dpio_phy. (Imre)
    Remove leftovers from previous version. (Imre)

v5: Actually git add the changes.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476863940-6019-1-git-send-email-ander.conselvan.de.oliveira@intel.com
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_dpio_phy.c
drivers/gpu/drm/i915/intel_dpll_mgr.c