[globalisel][tablegen] Require that all registers between instructions of a match...
authorDaniel Sanders <daniel_l_sanders@apple.com>
Wed, 17 May 2017 12:43:30 +0000 (12:43 +0000)
committerDaniel Sanders <daniel_l_sanders@apple.com>
Wed, 17 May 2017 12:43:30 +0000 (12:43 +0000)
commited205a090db1e6aca740e29a9bb54c589df81f0e
treed2d19f621371d28ed5ec2826d87c44363995eb17
parenteafa4aa91023c48c5742b82f8d92841f78c0c4cc
[globalisel][tablegen] Require that all registers between instructions of a match are virtual.

Summary:
Without this, it's possible to encounter multiple defs for a register.

This is triggered by the current version of D32868 when applied to trunk.

Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls

Reviewed By: qcolombet

Subscribers: llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D32869

llvm-svn: 303253
llvm/test/TableGen/GlobalISelEmitter.td
llvm/utils/TableGen/GlobalISelEmitter.cpp