mmc: renesas_sdhi: add quirk for broken register layout
authorWolfram Sang <wsa+renesas@sang-engineering.com>
Thu, 6 Oct 2022 19:04:50 +0000 (21:04 +0200)
committerUlf Hansson <ulf.hansson@linaro.org>
Wed, 7 Dec 2022 12:22:36 +0000 (13:22 +0100)
commitec9e80ae1719de541c719116a1ca0a0c70e9240c
treebbfdb6e1afde22fe228229e8400c1361944a396b
parentaf728d7ae20483add9f8d3c81280dc6298a0aa2e
mmc: renesas_sdhi: add quirk for broken register layout

Some early Gen3 SoCs have the DTRANEND1 bit at a different location than
all later SoCs. Because we need the bit soon, add a quirk so we know
which bit to use.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221006190452.5316-5-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/renesas_sdhi.h
drivers/mmc/host/renesas_sdhi_internal_dmac.c