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RISC-V: Add initial StarFive JH7100 device tree
authorEmil Renner Berthing <kernel@esmil.dk>
Sun, 10 Oct 2021 14:48:27 +0000 (16:48 +0200)
committerEmil Renner Berthing <kernel@esmil.dk>
Thu, 16 Dec 2021 16:24:23 +0000 (17:24 +0100)
commitec85362fb121d0297b9f3bb56816ea6282c34fda
treea71e08b3678a04b80def219a2e59842524696477tree | snapshot
parentb0ad20a3b64bf653a717860819691b262c0b2a2bcommit | diff
RISC-V: Add initial StarFive JH7100 device tree

Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This
is a test chip for their upcoming JH7110 SoC.

The CPU and cache data is based on the device tree in the vendor u-boot
port.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
arch/riscv/boot/dts/starfive/jh7100.dtsi [new file with mode: 0644] blob
Domain: System / Kernel;