dt-bindings: riscv: fix underscore requirement for multi-letter extensions
authorConor Dooley <conor.dooley@microchip.com>
Mon, 5 Dec 2022 17:44:59 +0000 (17:44 +0000)
committerPalmer Dabbelt <palmer@rivosinc.com>
Fri, 6 Jan 2023 18:31:09 +0000 (10:31 -0800)
commitec64efc4966edf19fa1bc398a26bddfbadc1605f
treefcbf016b4b2f81a2b67e8fc53f0978ad76dbaa15
parent9abf2313adc1ca1b6180c508c25f22f9395cc780
dt-bindings: riscv: fix underscore requirement for multi-letter extensions

The RISC-V ISA Manual allows the first multi-letter extension to avoid
a leading underscore. Underscores are only required between multi-letter
extensions.

The dt-binding does not validate that a multi-letter extension is
canonically ordered, as that'd need an even worse regex than is here,
but it should not fail validation for valid ISA strings.

Allow the first multi-letter extension to appear immediately after
the single-letter extensions.

Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022
Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221205174459.60195-2-conor@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Documentation/devicetree/bindings/riscv/cpus.yaml