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[VE] Support I32/F32 registers in assembler parser
authorKazushi (Jam) Marukawa <marukawa@nec.com>
Tue, 2 Jun 2020 08:22:30 +0000 (10:22 +0200)
committerSimon Moll <simon.moll@emea.nec.com>
Tue, 2 Jun 2020 08:22:45 +0000 (10:22 +0200)
commitec2e9ce73e6c2d70523f7e51a23bf07f998ebecd
tree25ba300e01ba6da10095c815144870cf5b110b6atree | snapshot
parent5b8c1ed2c802d3ae016363bab6d1e117b09ecdc9commit | diff
[VE] Support I32/F32 registers in assembler parser

Summary:
Support I32/F32 registers in assembler parser and add regression tests of LD/ST
instructions.

Differential Revision: https://reviews.llvm.org/D80777
llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp diff | blob | history
llvm/test/MC/VE/LD.s [new file with mode: 0644] blob
llvm/test/MC/VE/ST.s [new file with mode: 0644] blob
Domain: System / Toolchain;