author | Luke Lau <luke@igalia.com> | |
Wed, 1 Mar 2023 18:25:48 +0000 (18:25 +0000) | ||
committer | Luke Lau <luke@igalia.com> | |
Sun, 2 Apr 2023 15:47:44 +0000 (16:47 +0100) | ||
commit | ec26c9cdc002bdbf247eac0b2563f44f5e90e840 | |
tree | 37bf855cbe0aa28eba02c6ef1a234a0082f81d8f | tree | snapshot |
parent | ceff9524f92445b3110fb79f0d6239713b5df153 | commit | diff |
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | diff | blob | history | |
llvm/lib/Target/RISCV/RISCVISelLowering.h | diff | blob | history | |
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | diff | blob | history | |
llvm/test/CodeGen/RISCV/O3-pipeline.ll | diff | blob | history | |
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll | diff | blob | history | |
llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll | [new file with mode: 0644] | blob |
llvm/test/Transforms/InterleavedAccess/RISCV/lit.local.cfg | [new file with mode: 0644] | blob |
llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll | [new file with mode: 0644] | blob |
llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll | [new file with mode: 0644] | blob |