review.tizen.org Git - platform/upstream/coreclr.git/commit

author	mikedn <onemihaid@hotmail.com>
	Tue, 17 Apr 2018 01:09:32 +0000 (04:09 +0300)
committer	Jan Kotas <jkotas@microsoft.com>
	Tue, 17 Apr 2018 01:09:32 +0000 (18:09 -0700)
commit	ebec98d73014de4cb9e2296c61c292845ae65145
tree	4af8354d3417c640cb4cba409a748c708e22b3af	tree \| snapshot
parent	c9c401b81d7bdeb3d5932df117266caa0da5c32c	commit \| diff

Update memory histogram buckets (#15206)

Use values that are more likely to match CPU cache sizes (e.g. L1 = 32K and L2 = 256K)